Does "Channel Conflicts" chapter from "Programming Guide" still apply to the new architecture? In other words, how is logical to physical address translation implemented?
Yes, it still does apply, but it's a lot more complicated on chips that don't have power-of-2 memory bus width (i.e. HD79xx cards). For GPUs with 4 or 8 memory channels, expect similar behavior as documented.
Yes, it still does apply, but it's a lot more complicated on chips that don't have power-of-2 memory bus width (i.e. HD79xx cards). For GPUs with 4 or 8 memory channels, expect similar behavior as documented.
