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sema
Journeyman III

Does anyone understand the mention of DH and BH in table 1-12 in AMD64 Architecture Programmer’s Manual Volume 3?

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I'm looking at table 1-12 in "AMD64 Architecture Programmer’s Manual Volume 3: General-Purpose and System Instructions" revision 3.21 (Picture attached). It mentions DH and BH in the base register column for ModRM SIB adressing. Does anyone know if that means that there's actually a way to do ModRM SIB addressing with byte registers?

-SEMA

P.S.: Could a mod please move this to an appropriate place? There seems any number of graphics related forums, but no CPU forums, but surely that must just be me going blind! 🙂

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jtrudeau
Staff
Staff

Re: Does anyone understand the mention of DH and BH in table 1-12 in AMD64 Architecture Programmer’s Manual Volume 3?

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Hey, to my complete astonishment, I have learned what the GH refers to. I don't know why that information is actually presented in the manual, but it is an acronym for Greyhound, and references latencies in that architecture. The term has not been used for several years. A google search for "AMD Greyhound" will yield results dating around 2006/2007.

(As an aside - interesting the thread of person to person that question followed through our engineering team until it landed on someone who knew. I'm always fascinated by how minds network.)

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jtrudeau
Staff
Staff

Re: Does anyone understand the mention of DH and BH in table 1-12 in AMD64 Architecture Programmer’s Manual Volume 3?

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Actually, this is as good a spot as any - you are not blind. The primary focus of the forum IS  GPU and graphics programming, and the tools to get that done. That is NOT all encompassing, hence "General Discussions."

That being said, I'll see what I can track down as to your specific question. This may take some time.

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sema
Journeyman III

Re: Does anyone understand the mention of DH and BH in table 1-12 in AMD64 Architecture Programmer’s Manual Volume 3?

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jtrudeau wrote:



That being said, I'll see what I can track down as to your specific question. This may take some time.


Thanks 🙂   Don't worry, I've got time. But if you do manage get hold of a CPU expert I'd also be very curious to know the differences between the "Latencies" and "GH Latencies" columns in the "Software Optimization Guide for AMD Family 15h Processors" revision 3.08. I tried emailing your support department about it once, but they wanted me to start up a company, register as a developer and sign a confidentiality agreement 😞    Which seems kind of overkill for a retired hobby programmer, and considering the information is already public, only the meaning of "GH" isn't mentioned.

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jtrudeau
Staff
Staff

Re: Does anyone understand the mention of DH and BH in table 1-12 in AMD64 Architecture Programmer’s Manual Volume 3?

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Just checking in. Have not forgotten, someone who works on a different compiler team is now trying to track this down. Appreciate your patience.

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sema
Journeyman III

Re: Does anyone understand the mention of DH and BH in table 1-12 in AMD64 Architecture Programmer’s Manual Volume 3?

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Thanks for your efforts, it's appreciated 🙂

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jtrudeau
Staff
Staff

Re: Does anyone understand the mention of DH and BH in table 1-12 in AMD64 Architecture Programmer’s Manual Volume 3?

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And in the end, I can't find anyone who can comment or answer your initial question, which is: Does anyone know if that means that there's actually a way to do ModRM SIB addressing with byte registers?

Sorry, no joy in mudville on this one.

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sema
Journeyman III

Re: Does anyone understand the mention of DH and BH in table 1-12 in AMD64 Architecture Programmer’s Manual Volume 3?

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Oh well, tanks for trying. I must admit I'm inclined to think it might be a simple copy and paste error. I just don't see how it would be encoded.

You didn't stumble on anyone who'd be willing to explain the meaning of "GH Latencies" to me without requiring me to go through the entire legal circus?

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jtrudeau
Staff
Staff

Re: Does anyone understand the mention of DH and BH in table 1-12 in AMD64 Architecture Programmer’s Manual Volume 3?

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I was focused on the underlying question. It just dawned on me, although not working on this, I have a guy with a strong compiler background I can ping.... stay tuned.

(As an aside, having once written extensive technical docs, NEVER NEVER NEVER use an acronym without explaining it. Bad dog. Bad, bad dog.)

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jtrudeau
Staff
Staff

Re: Does anyone understand the mention of DH and BH in table 1-12 in AMD64 Architecture Programmer’s Manual Volume 3?

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Hey, to my complete astonishment, I have learned what the GH refers to. I don't know why that information is actually presented in the manual, but it is an acronym for Greyhound, and references latencies in that architecture. The term has not been used for several years. A google search for "AMD Greyhound" will yield results dating around 2006/2007.

(As an aside - interesting the thread of person to person that question followed through our engineering team until it landed on someone who knew. I'm always fascinated by how minds network.)

View solution in original post

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sema
Journeyman III

Re: Does anyone understand the mention of DH and BH in table 1-12 in AMD64 Architecture Programmer’s Manual Volume 3?

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What's even more astonishing is that there's no mention of Greyhound or GH in "Software Optimization Guide For AMD Family 10h And 12h Processors (2011-02-14 - 3.13)" or "Software Optimization Guide For AMD Family 15h Processors (2012-01-08 - 3.06)"! So someone added the information some 5 to 6 years after it was relevant, if indeed it ever was relevant. Bet there's an interesting story there somewhere 🙂

Anyway, thanks for your effort 🙂

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