Hi all,
I'm trying to implement a basic Vitis RTL kernel flow using SystemVerilog as a learning step before moving to full acceleration on the Alveo U280. My current setup uses a custom platform (VCK190, Linux, Cortex-A72) just to test compilation and host-kernel integration.
What I'm Doing:
Writing a minimal RTL kernel (axi_wire_kernel.sv) with a simple AXI-Lite input and ap_ctrl_hs handshake.
Created a kernel.xml to describe the AXI-Lite interface.
Trying to compile the kernel using v++ to generate a .xo file.
What I’ve Done:
Created a custom platform in Vitis 2023.2 (exported .xpfm)
Placed my .sv and kernel.xml in C:\Users\bhami\wire_wrapper
Tried running the following:
v++ -c -t hw --platform C:/Users/bhami/vitis_workspace/platform/export/platform/platform.xpfm -k axi_wire_kernel -o axi_wire_kernel.xo axi_wire_kernel.sv
The Problem:
v++ complains about --mode rtl or fails silently when run from Vitis IDE terminal or PowerShell.
I suspect my environment isn’t set up correctly (missing settings64.bat?).
Not sure how to compile System Verilog-based RTL kernels properly in this flow.
What I Need:
Correct method/environment to compile RTL kernels with v++
Do I need Vivado’s settings64.bat even if I'm in a Vitis terminal?
Can I avoid needing the full U280 .xpfm just for now?
Am I missing a required .cfg or other metadata file?
Any guidance would be appreciated. Just trying to validate the flow before scaling up.
