Adaptive SoC & FPGA Discussions

[fpgauser]

Hi everyone,

I'm currently migrating a legacy project from ISE to Vivado, and I'm facing consistent issues with IP cores after the initial synthesis.

The first time I open the project and run synthesis in Vivado, it completes successfully. However, as soon as I make any change or simply run synthesis again, I start getting errors related to missing or black-box IP cores (e.g., FIFO Generator, Clock Wizard, etc.).

Here’s what I’ve tried so far:

• Re-generating output products for all IP cores (Right click → Regenerate Output Products).

• Resetting the IP cores and generating them again.

• Cleaning the project files (.Xil, runs/, cache/, etc.) and restarting Vivado.

• Ensuring that all IP cores are added correctly in the project sources.

• Checking the synthesis and elaboration settings in Project Settings.

None of these steps have resolved the issue. It seems like Vivado somehow "forgets" or loses track of the IP cores after the first synthesis.

Has anyone experienced this behavior after migrating a project from ISE? Could this be related to IP cache, file references, or project settings? Any ideas on how to fix this permanently?

Thanks in advance!

[fpgauser]

Please note that the project was originally created and compiled under Linux, but I am now trying to compile it on a Windows machine. I suspect this platform change might also be contributing to the issues I'm facing with the IP cores, especially regarding file paths, line endings, or OS-specific caching behavior.

[fpgauser]

Thank you very much for the suggestion. I will give it a try and see if it resolves the issue.

[goodplay]

It would be better to post on the separate dedicated support site, https://adaptivesupport.amd.com/s/?language=en_US