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[rick_weber]

So, if I read the documentation correctly, there are 5 stream cores per thread processor. All five them can perform one integer/floating point operation per cycle, with the T-unit additionally being able to perform transcendental operations. However, there is no float5 construct and registers are only 128 bit. Does that mean the following can be issued in a single VLIW word?

add r2, r0, r1
add r5.x, r4.x, r3.x 

[MicahVillmow]

It could be possible based on the GPR read and cycle restrictions as specified in section 4.7 of the R600_Instruction_Set_Architecture.pdf. There is no float5 construct because there are 4 GPR memory banks each 32bits wide and float4 directly map to that. See mainly 4.7.4 and figure 4.3

[rick_weber]

Ok, thanks!