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[givenchy]

Hi,

I could see the latency about global memory in manual.

But I don't see the private memory latency in manual, NVIDIA shows the latency "zero cycle or read after right(24cycle) "  in its manual .

And how about AMD OpenCL ?

Regards.,

Thanks

[realhet · Accepted solution]

Hi,

There's no such latency on AMD. In every cycle it can read 3 regs and write 1 reg.

The only penalty I know is when a vector instruction that writes into a scalar reg is followed by a scalar instruction. That could be 1 cycle penalty but the compiler will avoid this anyways.