I was wondering if it was possible for an IPI to "overtake" a memory write.
1. CPU A writes some global variable (and the write happens to stay in the write buffer for a long time)
2. CPU A sends an IPI to CPU B
3. CPU B's IPI ISR reads the global variable
Is it theoretically possible in this scenario that the write buffer of CPU A has not been drained to the cache/memory when CPU B takes the interrupt and thus reads an old value of the variable?
I.e. is an explicit synchronisation instruction needed?
I couldn't find any information on that in chapter 7 (Memory System) of the Programmer's Manual Vol. 2. And while chapter 7.5.1 (Write Buffering) says that interrupts are serializing events that drain the write buffer, I suspect this only refers to the CPU receiving the interrupt, not the one sending it.