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[ryta1203]

1. Is the cache on the AMD GPUs used for decreasing latency or only increasing bandwidth?

2. The profiler doesn't seem to have a cache hit/miss counter? Why not? CAL/IL has one built in, so I'm curious why this doesn't have it considering the amount of VFetches used (thus using cache, correct?)

[gaurav_garg]

1. Is the cache on the AMD GPUs used for decreasing latency or only increasing bandwidth?

I think the design goal for GPU caches is only increase in memory bandwidth. As a side effect of being on chip, caches have lower latency too. Not sure about numbers though.

2. The profiler doesn't seem to have a cache hit/miss counter? Why not? CAL/IL has one built in, so I'm curious why this doesn't have it considering the amount of VFetches used (thus using cache, correct?)

I looked at the ISA generted by MMM sample shipped with SDK. It contains VFETCH instruction, but this is not cached. For caching, the fetch clause has to be TEX_VC or TEX_TC. Right now, it is only TEX.

[ryta1203]

Guarav,

  This doesn't seem to be the case though, according to Micah:

http://forums.amd.com/devforum/messageview.cfm?catid=390&threadid=127466&highlight_key=y&keyword1=vf...

So, if there are some cases which use cache then it would be nice if the profiler reported the cache usage.

[gaurav_garg]

I am still not convinced that UAV reads are cached right now. Please see my reply on the same thread.

[ryta1203]

Gaurav,

  Ok, if you are correct, my guess is that cached global memory might be supported in the future, in which case it would be nice if it was profiled.