Welcome to the fourth installment of the Ryzen Community Updates! If you’re checking into this series for the first time, this is where we let our community know about all the exciting updates that are on their way for the AMD Ryzen™ processor. We’ve covered a lot of ground in a short amount of time: game updates, new Windows® power plans, stability improvements, feature additions and much more. Today’s update is the one many of you have been most excited about: the AGESA that focuses on overclocked memory. There’s some great news for IOMMU/ACS users, too!
What is an “AGESA”?
AGESA is an acronym that stands for “AMD Generic Encapsulated System Architecture.” As a brief primer, the AGESA is responsible for initializing AMD x86-64 processors during boot time, acting as something of a “nucleus” for the BIOS for your motherboard. Motherboard vendors take the core capabilities of our AGESA updates and build on them with their own “secret sauce” to create the BIOS files you download and flash. Today, the BIOS files for AMD AM4 motherboards are largely based on AGESA version 18.104.22.168.
Beginning this month, as we promised to you, we began beta testing a new AGESA (v22.214.171.124) that is largely focused on aiding the stability of overclocked DRAM (>DDR4-2667). We are now at the point where that testing can begin transitioning into release candidate and/or production BIOSes for you to download. Depending on the QA/testing practices of your motherboard vendor, full BIOSes based on this code could be available for your motherboard starting in mid to late June. Some customers may already be in luck, however, as there are motherboards—like my Gigabyte GA-AX370-Gaming5 and ASUS Crosshair VI—that already have public betas.
Starting With Virtualization
If you’re the kind of user that just needs (or loves!) virtualization every day, then AGESA 126.96.36.199-based firmware will be a blessing for you thanks to fresh support for PCI Express® Access Control Services (ACS). ACS primarily enables support for manual assignment of PCIe® graphics cards within logical containers called “IOMMU groups.” The hardware resources of an IOMMU group can then be dedicated to a virtual machine.
This capability is especially useful for users that want 3D-accelerated graphics inside a virtual machine. With ACS support, it is possible to split a 2-GPU system such that a host Linux® OS and a Windows VM both have a dedicated graphics cards. The virtual machine can access all the capabilities of the dedicated GPU, and run games inside the virtual machine at near-native performance.
This is certainly a complicated setup for most users, but I have no doubt that there will be a whole lot of you enthusiastically nodding at this news. We’re grateful for your feedback and your patience, and we hope the new support for ACS serves you well.
What's Next For Memory
AGESA 188.8.131.52 officially adds 26 new parameters that can improve the compatibility and reliability of DRAM, especially for memory that does not follow the industry-standard JEDEC specifications (e.g. faster than 2667, manual overclocking, or XMP2 profiles).
The following table spells out all the new parameters, and provides a few words on what they do. Keeping in mind that this is overclocking territory, manual or automated control of these parameters should nevertheless make it a little more straightforward to use DDR4-3200 modules—or faster if you have the talent!1
|Memory clocks||Added dividers for memory clocks up to DDR4-4000 without refclk adjustment. Please note that values greater than DDR4-2667 is overclocking. Your mileage may vary (as noted by our big overclocking warning at the end of this blog).||133.33MT/s intervals (2667, 2933, 3067, 3200, 3333, 3466, 3600, 3733, 3866, 4000)|
|Command rate (CR)||The amount of time, in cycles, between when a DRAM chip is selected and a command is executed. 2T CR can be very beneficial for stability with high memory clocks, or for 4-DIMM configurations.||2T, 1T|
|ProcODT (CPU on-die termination)||A resistance value, in ohms, that determines how a completed memory signal is terminated. Higher values can help stabilize higher data rates. Values in the range of 60-96 can prove helpful.||Integer values (ohms)|
|tWCL/tWL/tCWL||CAS Write Latency, or the amount of time it takes to write to the open memory bank. WCL is generally configured equal to CAS or CAS-1. This can be a significant timing for stability, and lower values often prove better.||Integer values (cycles)|
|tRC||Row cycle time, or the number of clock cycles required for a memory row to complete a full operational cycle. Lower values can notably improve performance, but should not be set lower than tRP+tRAS for stability reasons.||Integer values (cycles)|
|tFAW||Four activation window, or the time that must elapse before new memory banks can be activated after four ACTIVATE commands have been issued. Configured to a minumum 4x tRRD_S, but values >8x tRRD_S are often used for stability.||Integer values (ns)|
|tWR||Write recovery time, or the time that must elapse between a valid write operation and the precharging of another bank. Higher values are often beneficial for stability, and values < 8 can quickly corrupt data stored in RAM.||Integer values (ns)|
Voltage for the DDR4 PHY on the SoC. Somewhat counterintuitively, lowering VDDP can often be more beneficial for stability than raising CLDO_VDDP. Advanced overclockers should also know that altering CLDO_VDDP can move or resolve memory holes. Small changes to VDDP can have a big effect, and VDDP cannot not be set to a value greater than VDIMM-0.1V (not to exceed 1.05V). A cold reboot is required if you alter this voltage.
Sidenote: pre-184.108.40.206 BIOSes may also have an entry labeled “VDDP” that alters the external voltage level sent to the CPU VDDP pins. This is not the same parameter as CLDO_VDDP in AGESA 220.127.116.11.
|Integer values (V)|
|tRDWR / tWRRD||Read-to-write and write-to-read latency, or the time that must elapse between issuing sequential read/write or write/read commands.||Integer values (cycles)|
|tRDRD / tWRWR||Read-to-read and write-to-write latency, or the time between sequential read or write requests (e.g. DIMM-to-DIMM, or across ranks). Lower values can significantly improve DRAM throughput, but high memory clocks often demand relaxed timings.||Integer values (cycles)|
|Geardown Mode||Allows the DRAM device to run off its internally-generated ½ rate clock for latching on the command or address buses. ON is the default for speeds greater than DDR4-2667, however the benefit of ON vs. OFF will vary from memory kit to memory kit. Enabling Geardown Mode will override your current command rate.||On/Off|
|Rtt||Controls the performance of DRAM internal termination resistors during nominal, write, and park states.||Nom(inal), WR(ite), and Park integers (ohms)|
|tMAW||Maximum activation window, or the maximum number of times a DRAM row can be activated before adjacent memory rows must be refreshed to preserve data.||Integer values (cycles)|
|tMAC||Maximum activate count, or the number of times a row is activated by the system before adjacent row refresh. Must be equal to or less than tMAW.||Integer values (cycles)|
|tRFC||Refresh cycle time, or the time it takes for the memory to read and re-write information to the same DRAM cell for the purposes of preserving information. This is typically a timing automatically derived from other values.||Integer values (cycles)|
|tRFC2||Refresh cycle time for double frequency (2x) mode. This is typically a timing automatically derived from other values.||Integer values (cycles)|
|tRFC4||Refresh cycle time for quad frequency (4x) mode. This is typically a timing automatically derived from other values.||Integer values (cycles)|
|tRRD_S||Activate to activate delay (short), or the number of clock cycles between activate commands in a different bank group.||Integer values (cycles)|
|tRRD_L||Activate to activate delay (long), or the number of clock cycles between activate commands in the same bank group.||Integer values (cycles)|
|tWR||Write recovery time, or the time that must elapse between a valid write operation and the precharging of another bank. Higher values are often better for stability.||Integer values (ns)|
|tWTR_S||Write to read delay (short), or the time between a write transaction and read command on a different bank group.||Integer values (cycles)|
|tWTR_L||Write to read delay (long), or the time between a write transaction and read command on the same bank group.||Integer values (cycles)|
|tRTP||Read to precharge time, or the number of clock cycles between a READ command to a row and a precharge command to the same rank.||Integer values (cycles)|
|DRAM Power Down||Can modestly save system power, at the expense of higher DRAM latency, by putting DRAM into a quiescent state after a period of inactivity.||On/Off|
Until next time
What are you interested in hearing more about in our next AMD Ryzen Community Update? Let us know on Twitter @AMDRyzen!
Robert Hallock is a technical marketing guy for AMD's CPU division. His postings are his own opinions and may not represent AMD’s positions, strategies or opinions. Links to third party sites are provided for convenience and unless explicitly stated, AMD is not responsible for the contents of such linked sites and no endorsement is implied.
1. WARNING: Overclocking memory will void any applicable AMD product warranty, even if such overclocking is enabled via AMD hardware and/or software. This may also void warranties offered by the system manufacturer or retailer or motherboard vendor. Users assume all risks and liabilities that may arise out of overclocking memory, including, without limitation, failure of or damage to RAM/hardware, reduced system performance and/or data loss, corruption or vulnerability. GD-112