• GPU demand paging

    I'm trying to research whether GPU demand paging is possible with the nowadays hardware. Say, I'd like to store the demanded data on DRAM or another VRAM; The accesses to the local VRAM (by VA) are intercepted and the...
    hyu
    last modified by hyu
  • AMD and AI

    I think you should have a general AI forum where people can post general ideas and algorithms about AI.  Like the one Numenta have, not one as closed down and excluding like Intel's forums.  I would sugges...
    seanc4s
    last modified by seanc4s
  • Use AMD GPUs in brute forcing

    Hello, I'm a new developer and decided to go from writing small good for nothing programs for practice, to actually making something useful, a RAR-PDF etc password recovery tool. The original plan was to make a simple...
    rexpatrum
    last modified by rexpatrum
  • How can my Ryzen 1700 be faster than an Intel 4790K in single thread work

    Hei guys, I am writing you today because I had some surprising findings after optimizing some hot loops for my Ryzen 1700. The specific code was a deformer for Autodesk Maya, the deformer takes as an input a polygonal...
    giordi91
    last modified by giordi91
  • Why are there only 16 GPR registers when 32 ZMM/YMM/XMM registers exist?

    A simple question; Why are there only 16 GPR registers in modern CPU designs, when there are 32 ZMM registers (2048 bytes of space!) on these systems? (Assuming AVX512) Looking at how ZMM/YMM/XMM are currently handled...
    moonheart08
    last modified by moonheart08
  • Multicore numerical optimization

    Since AMD CPU's now have so many cores you could try these numerical optimization algorithms (in Java) with them: https://github.com/S6Regen/Cisco
    seanc4s
    last modified by seanc4s
  • Research into DVI connections

    Hello, I am not a developer; I am just mad. I was encouraged to post here by AMD Global Customer Care. I wrote about DVI connections to put my pain into a form that may provoke or inform others. I am criticizing cable...
    dviguy
    last modified by dviguy
  • Broken links for old ATI SDKs source code archives

    I have been trying to find valid source code download links for some of the old ATI tech demos and SDKs, but everything seems broken:   Archive links: https://web.archive.org/web/20121117022642/http://develope...
    jpp
    last modified by jpp
  • WSL driver support

    I would like an official answer from AMD on this. I'm not interested in hearing people's opinion. Only facts and theories that are constructive to this thread if you're not from AMD. With the support of AF_Unix on Win...
    wsluser
    last modified by wsluser
  • World Health Organization - Gaming Disorder

    This is a reprint of an email I sent to the World Health Organization (WHO) that I thought you all might be interested in.  If the new classification causes damages to AMD's business, I would think AMD might be d...
    tim.reago
    last modified by tim.reago
  • Compatible cooling fan for server graphics card?

    I am thinking of buying S9150 for OpenCL use. One problem is that I do not own any rack type case. I do think that my workstation's internal air flow is somewhat 'okay', not as close to that of the normal rack mounted...
    ep-98d
    last modified by ep-98d
  • Ideas For AMD to Succeed...

    Hi Devs!     Mike H. here with some ideas for AMD, so they can get back  into the game with their graphics cards and succeed and win in the market between AMD and Nvidia. I'll post a few short ideas by...
    mikehfan
    last modified by mikehfan
  • Does new CPU Profiler uProf supports event L3PMCx06 [L3 Miss] ?

    Team, Im trying to profile an application in my Ryzen and would be really useful to have L3 misses data for the application. The thing is that when I try to capture this counter it gives me an error and the documentat...
    jsomarri
    last modified by jsomarri
  • Strange post on Nvidia forum (secret to beating the green team)?

    I found a strange post on the Nvidia forum, it seems like someone named "Venturi" found a way to make 4 way SLI scale well, using dual CPUs. If AMD could encourage dual configurations for Rizen and make motherboard ma...
    maverick11
    last modified by maverick11
  • Maximum surface size lower for DirectDraw than Direct3D?

    I posted this question a while ago in the newcomers forum, which I guess no-one reads...   I'm using an AMD FirePro W5100 on Windows 10 x64 1703. Driver version 21.19.384.0. The maximum hardware surface size ...
    donuts
    created by donuts
  • AMD RAID Bottom

    Dear AMD, Dear DevGurus,   I'm looking for the API / Software Developers Kit of the new chipset with AMD RAID Bottom solution to access hard disk drives / SSDs configured into RAID arrays (by ATA pass through f...
    janosmathe
    created by janosmathe
  • How many LUT (Lookup Tables) has a Radeon HD 6970?

    Hi there, I parsed all the specifications on the AMD website but I couldn't find how many Lookup Tables (LUT) are included within the AMD Radeon HD 6970. Can anyone help me with this? I need those because I'm using...
    chiefra
    last modified by chiefra
  • 5-Level Paging and 57-bit Linear Address? Stop that stupid!

    In Intel's 5-Level Paging and 5-Level EPT white paper, they planed to introduce another level paging mechanism, PML5, extending the linear address from 48-bit to 57-bit (57-bit, not 64-bit!!!!!). What that stupid thin...
    mr.unknown
    last modified by mr.unknown
  • Disabling the DRAM Auto-Refresh During Boot

    Dear AMD Developer Community,   I am using Coreboot to boot an AMD A6-5400K processor on an ASUS F2A85-M motherboard. During boot I would like to disable the auto-refresh of the DDR3 DRAM to measure its retentio...
    bkc177
    last modified by bkc177
  • 2D Laplacian memory tiling

    Hello everyone,   I have a bit of a doubt and I hope someone can help me here. I've seen several examples for the 5-point stencil of the 2D laplacian, but usually in global memory (which I've already implemented...
    nefastious
    last modified by nefastious